Polling and Interrupt allow the CPU to stop what it is currently doing and to answer the most important task. Polling and Interrupt are different from each other in many respects. But the base point that distinguishes Polling and Interrupt from that polling the CPU continues to check I / O devices at regular intervals if it needs CPU service while in interrupt, the I / O device shuts down the CPU and tells the CPU that it needs CPU service. I have discussed some differences between Interruption and Polling in the comparison chart below, please take a look.
|Basic||Device notifies the CPU that it requires CPU attention.||The CPU constantly checks the status of the device, regardless of whether it requires attention from the CPU.|
|Mechanism||An interrupt is a hardware mechanism.||Polling is a protocol.|
|maintenance||Stop the device service manager.||The CPU serves the device.|
|Indication||The interrupt request line indicates that the device needs maintenance.||The bit ready for Comand indicates that the device needs maintenance.|
|processor||CPU disturbed only when a device needs maintenance, saving CPU cycles.||The CPU has to wait and see if a device needs maintenance that wastes many CPU cycles.|
|event||An interrupt can occur at any time.||The CPU polls devices at regular intervals.|
|Efficiency||Interruption becomes inefficient when devices continue to repeatedly interrupt the CPU.||Polling becomes inefficient when the CPU rarely finds a device ready for service.|
|Example||Let the bell ring and then open the door to check who has arrived.||He continues to open the door to check if anyone has come.|
Definition of interruption
An interrupt a hardware mechanism which allows the CPU to detect that a device requires its attention. The CPU has one interrupt request line wire that is controlled by the CPU after executing each individual instruction. When the CPU detects an interrupt signal on the interrupt request line, the CPU interrupts the currently running activity and responds to the sending of interrupts by the I / O device by passing the control to the interrupt handler . The interrupt handler resolves the interruption by assisting the device.
Although the CPU is not aware of when an interrupt will occur because it can occur at any time, but must respond to the interrupt whenever it occurs.
When the interrupt handler finishes executing the interrupt, the CPU resumes execution of the activity that stopped to respond to the interrupt. Software, hardware, user, some errors in the program, etc. They can also generate an interrupt. Interrupts CPU nature management leads to multitaskingthat is, a user can perform a number of different tasks at the same time.
If more than one interrupt is sent to the CPU, the interrupt handler helps handle interrupts that are awaiting processing. When the interrupt handler comes activated from receiving an interrupt, assigns there priority interrupts waiting to be processed by the CPU and organize them into one tail for assistance.
As we have seen in interrupts, input from the I / O device can come at any time by requiring the CPU to process it. Polling a protocol which notifies the CPU that a device requires its attention. Unlike the interrupt, where the device indicates to the CPU that it needs CPU processing, in the polling CPU it continues to to ask to the I / O device if it needs CPU processing.
The CPU tests continuously all devices connected to it to detect if a device requires CPU attention. Every device has a bit of command which indicates the status of that device, that is, if it has any command to execute or not from the CPU. If the command bit set to 1, then it has some command to execute otherwise if the bit 0, so it has no commands. The CPU has a busy bit which indicates the status of the CPU, regardless of whether it is busy or not. If the busy bit set to 1, then busy executing the command of some device, otherwise 0 .
- When a device has a command that must be executed by the CPU, it continuously checks the CPU busy bit until it becomes clear (0).
- When the busy bit becomes clear, the device sets the write bit in its command register and writes a byte in the data output register.
- Now the device sets (1) the bit ready for the command.
- When the CPU checks the bit ready for command of the devices and finds it set (1), sets (1) its bit occupied.
- The CPU then reads the device command log and executes the device command.
- After executing the command, the CPU clears (0) the ready-to-use bit, the device error bit to indicate the correct execution of the device command and also clears (0) its busy bit also to indicate that the CPU free to execute the command of some other device.
Key differences between interrupts and polling in the operating system
- In the event of an interrupt, the device notifies the CPU that it needs assistance while, in polling, the CPU repeatedly checks whether a device needs maintenance.
- Interrupt a mechanism hardware in how much CPU has a wire, an interrupt request line which signals the interruption. On the other hand, Polling a protocol who keeps checking i control bits to notify if a device has something to do.
- The interrupt handler manages the interrupts generated by the devices. On the other hand, in polling, the services of the CPU the device when they require.
- Interrupts are reported by interrupt request line . However, the bit ready for command indicates that the device needs maintenance.
- In interrupts, the CPU is disturbed only when a device interrupts it. On the other hand, in polling, the CPU wastes many CPU cycles by repeatedly checking the bit ready for command of each device.
- An interrupt can occur in any instant of time while, CPU continues to query the device a regular intervals .
- Polling becomes inefficient when the CPU continues to interrogate the device and rarely finds any device ready for maintenance. On the other hand, interrupts become inefficient when devices continue to interrupt CPU processing repeatedly.
Both polling and interrupts are effective in assisting I / O devices. But they can become inefficient under certain conditions as discussed above.